Thanks Julio of 3DSpotlight who sent me notification of his lowdown on the new naming scheme for SDRAM modules.
And now the blurb: The new naming system for SDRAM is no longer based on the number of clock cycles, indeed if this was the case I would be reviewing PC133/PC150 memory. Contrary to apparently popular belief, DDR RAM is no different in design to SDR SDRAM. The differences being data is transferred on both the rising and falling sides of the clock cycle, a different sized DIMM slot is used, and the chipset needs to support DDR. This does not mean you can put 184 pin DDR modules into 168 pin SDR DIMM slots or vice versa though.
The new naming system is based on an apparently more accurate statistic: the bandwidth. The bandwidth is found by multiplying the effective frequency (which in the case of DDR is twice the number of clock cycles) by the width of the memory (in the case of SDRAM this is 64 bit) and dividing the result by the number of bits per byte, which is always 8. You can use this technique to work out the speed of other memory, but beware RDRAM has eight bit registers rather than the 64 bit width on SDRAM.