Intel McKinley details leaked
Posted by configure on 01 February 2002 - 09:29 · no comments & 155 views
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In the presentation, Intel reveals details of its next generation McKinley 64-bit processor, which as we noted in a report on the Solid State Conference the other day, will use low latency level three cache design.
It will also use next generation non volatile memory.
And Intel claims McKinleys in the future will run at .13 micron and at 5GHz at normal room temperature, because of the low power circuits it will use.
The paper also shows details of its Ovonics based memory array architecture, which helps it create big caches in future generations of its 64-bit chips.
There's also a picture of McKinley which Intel says is due for release in the middle of 2002, and which started sampling during this month. Intel claims it will deliver between 1.5 to 2 times performance over existing Itanics.
As we have suggested earlier, McKinley will have a 3MB level three cache, with 64GB/s bandwidth for Level 2 cache - Intel will claim that's four times greater than proprietary designs. McKinley cache is 85 per cent efficient, Intel will claim.
The Inquirer found the PDFs freely available on Intel's site - with the links on the Sandpile forum, here. The second PDF with the die and the cache details is a big one - over 2MB.
UMC gets a big, committed customer, while AMD gets more capacity and access to cheaper manufacturing techniques. In July 2001, the company said it was on track to introduce 130 nanometer and SOI (silicon on insulator) technologies at Dresden. More to the point, it expected to reach 100 per cent production capacity at the end of 2001.
The UMC tie-in gives AMD the opportunity to increase CPU market share without having to shell out vast new sums. Remember, the company's Dresden plant was a crippling expense for several years. By 2003, AMD expects to have invested $2.3 billion in this factory.