WHEN CPUS start appearing using 90 nanometer technology, it gives the chip companies a lot more transistors to play with. So we presume that is why AMD, in a white paper on its web site which has escaped our notice before, talks about how a single processor with two Hammer cores could interface into a north bridge using the system request interface (SRI).
A diagram on page eight of the PDF, which you can find is truly ancient in CPU terms, but describes the process in some detail. Figure five also examines the command and data paths including internal bus widths between the CPU and the north bridge.
And while this is no announcement from AMD, it's clear that the design, in theory at least, allows Hammer to be scaled up to a second CPU core. Dual processors were talked about a lot this year, with one senior Intel executive hinting at the last Developer Forum that it might be possible to create Itaniums using dual cores, too.
View: AMD Eighth-Generation (pdf)
News source: The Inq
A diagram on page eight of the PDF, which you can find is truly ancient in CPU terms, but describes the process in some detail. Figure five also examines the command and data paths including internal bus widths between the CPU and the north bridge.
And while this is no announcement from AMD, it's clear that the design, in theory at least, allows Hammer to be scaled up to a second CPU core. Dual processors were talked about a lot this year, with one senior Intel executive hinting at the last Developer Forum that it might be possible to create Itaniums using dual cores, too.
View: AMD Eighth-Generation (pdf) News source: The Inq
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