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Facts & Assumptions about the Architecture of AMD Opteron and Athlon 64

Daniel Fleshbourne   on 31 December 2002 - 10:19 · 2 comments & 149 views

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An attentive reader has both pros and cons. On one hand, he/she usually gets the idea of the article. On the other hand, sometimes such readers guess what the author didn't mean to unveil.

A technical presentation is not a less odd thing. One one hand, they are anxious to tell you as much as possible about their product. But if everything is uncovered, then what to speak of at launch? Besides, in this case the competitors will get a chance to adjust their plans. That is why a poor marketer looks for a balance trying both to eat a fish and not to get his ears wet.

As you know, AMD keeps on promising to release new-generation processors based on the Hammer core - Athlon 64 and Opteron. The first is meant for the desktop market, while the other for the server sector. Now we will look into and analyze information we have about these processors.

As you remember, the new AMD's processor have several key elements:
  • x86-64 architecture
  • processor core
  • integrated memory controller
  • Hyper Transport based input/output bus

View: The full story
News source: Digital Life


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#1 nonick on 31 Dec 2002 - 11:17
man, if they didntr integrate the 'integrated memory controller' they'd have released the hammer ages ago! fix the damn problem will ya
#2 DrunkenMaster on 31 Dec 2002 - 19:05
The integration of the memory controller on the chip has been implemented as a way to increase the performace by reducing the latency of swapping memory through the registers on the CPU. If you've looked at the benchmarks on some websites, you'll notice that there is reduced latency per instruction in the Hammer on average by 1/8 to 1/10. This explains, in part, why in 32 bit mode the 1.2 GHz Hammer matces the P4 2.2.

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