New G4 roadmaps promise Apple harvest

While Apple watchers look for first sightings of the G5 chip, Motorola is taking the G4 into fertile territory. By this time next year three as yet unannounced versions of the G4 will dramatically boost internal bandwidth, support switched fabric interconnects, and will see the processor talk to memory at full bus speed, according to disclosures from Motorola sources.

According to Motorola sources, a tweaked version of the Apollo 7450 G4, the 7470, will be ready for volume production shortly after the end of Q2, in time for a summer ramp. The 7470 will be manufactured on a 0.13 micron process, allowing for a smaller die size with room for 512K of L2 cache, and support up to 4MB of DDR-SDRAM L3 cache.

The 7470 supports a modified bus protocol, MPX+, which supports double data transfer and which should effectively run at 266Mhz according to sources. The MPX+ bus retains MPX's 36-bit addressing lines, and is described as interim measure. Don't expect dramatic leaps in SMP scaling - two will remain the sweet spot. The 7470 should scale to 1.5MHz. In parallel development, Motorola is priming a cut-down 7470 labelled the 7460, which doesn't support L3 cache.

But the third addition to the G4 family, the 7500 - slated for volume production by this time next year, should steal some headlines. Like the 7470, the 7500 will be built to a .13 micron process, and will feature a 14 stage pipeline (11 integer).

The 7500 will be the first desktop processor to employ the RapidIO architecture to communicate with the system at 500Mhz. RapidIO is a switched fabric interconnect that mirrors the parallel Infiniband initiative: the former is endorsed by the embedded industry, the latter by big iron system vendors, so the two don't really overlap. But the move to a standard switch architecture away has been a long time coming: high-end systems use their own proprietary switches (in mainframe terminology, a "crossbar switch") or a combination of a bus and a switch.

In practical terms it will permit the the memory controller to be housed on the die, communicating at full clock speed. So potentially, there's no need for L3 on-die cache. With DDR-SDRAM at 266Mhz and heading for 333Mhz, this should result in a comfortable improvement in throughput.

News source: The Register

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