Samsung's Plan for Terabit Flash Memory

Researchers at Samsung, one of the leading producers of flash-memory chips, recently announced a new chip that can hold twice as much data as before, and without an increase in its footprint on a circuit board. They were able to double the data capacity by building chips with multiple layers of silicon, creating 3-D structures. At the International Electron Device meeting in San Francisco last week, lead researcher Soon-Moon Jung said that by combining today's chip-making processes with the new 3-D design, they could build a one-terabit flash chip composed of eight layers of silicon.

The researchers turned to a process previously used at Samsung to make 3-D stacks of static random-access memory. The process uses a high-quality, single-crystal silicon substrate to build the first layer of memory cells. That layer is then used as a foundation on which to build a second layer, also composed of single-crystal silicon.

Essentially, a single layer of flash is analogous to a parking lot: electrons fill up memory cells much as cars fill up parking spots. Adding another layer of silicon increases the data capacity just as a two-story parking garage can hold more cars than a one-story parking garage can.

Samsung's challenge, then, was to minimize the area that these windows take up by strategically distributing them, in much the same way that columns are used as structural supports in parking garages.

Another trick the researchers used, says Jung, was to simultaneously fabricate the wire interconnects used for communication between layers and beyond the chip. If the wires were added separately, the 3-D chips would be much more expensive to make, due to the extra steps involved in ensuring communication between layers.

Link: Press Release
View: Full Article @ Technology Review

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