TI to sample 65-nanometer chips in early 2005

Texas Instruments Inc. (TI) plans to sample a wireless product built with its 65-nanometer semiconductor manufacturing process technology in the first quarter of next year, the Dallas-based company said Monday. Offering details of its 65-nanometer CMOS (complementary metal oxide semiconductor) process, the company said that it expects the new technology will reduce leakage power from idle transistors, such as when a cell phone is in standby mode, by a factor of 1,000.

In recent months, 90-nanometer processors have been introduced and rolled out in PCs and wireless devices. The smallest track or gap width on a chip surface is measured in nanometers. A lower nanometer measurement means that semiconductors can be made that are physically smaller, and they also are faster, more powerful and efficient because more transistors can be packed into the smaller space. For instance, TI says that its 65-nanometer process will allow integration of hundreds of millions of transistors supporting analog and digital function in system on chip configurations.

News source: InfoWorld

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