Xeon Phi, Intel's new “co-processor” for supercomputing

The supercomputer and “high performance computing” (HPC) market is steadily growing, and Intel wants to cut a large piece of the cake with its new line of specifically tailored products named Xeon Phi.

The new Xeon Phi “co-processor” is the final stage of the Larrabee project, ie the idea to use the familiar x86 microarchitecture and instruction set to build a powerful, easily exploitable “processing unit” to couple with a more traditional CPU for executing highly parallelized workloads.

Intel now defines Larrabee as the Many Integrated Core Architecture (MIC), while Xeon Phi is the first commercial fruition of the aforementioned MIC technology: the “accelerating unit” will be first available at the end of 2012 with “Cascade”, the new supercomputing unit from Cray.

Every Xeon Phi-equipped PCIe card will mount several 22-nanometer (Ivy Bridge), x86 CPUs for a total of more than 50 computing cores and a “minimum” of 8 Gigabytes of GDDR5 RAM. “Beyond its compatibility with x86 programming models”, Intel’s press release says, the “Xeon Phi coprocessor will be visible to applications as an HPC-optimized, highly-parallel, separate compute node that runs its own Linux-based operating system independent of the host OS”.

Intel highlights how well its currently available line of Xeon CPUs performed in the most recent edition of the Top500 list ranking the world’s most powerful supercomputers, in which nearly 75% of the systems were equipped with thousands of processors from Santa Clara. With Xeon Phi, Chipzilla wants to secure its place among the HPC players against IBM’s Blue Gene supercomputing machines based on the Power architecture.

Source: Intel’s press release.

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9 Comments

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I'm not a wiz in this area so someone explain this to me. What's the point of using x86 cpu's for 'performance' on 64 bit systems? x86 can't load x64 assemblies, correct? Not to mention x64 is twice what x86 is, how does that equal performance even if you manage to allow it to process that information - it's twice the amount.

This all seems great but doesn't make any sense to me. I really need someone more versed in this to explain how using x86 processors in an x64 system helps when they can't process the information. To me it equates to having a bunch of people that only speak Chinese help you build a house when the instructions are written in English.

I have imagined running a low-power ARM/Atom CPU for the Operating System itself (eg: Kernel, Hardware I/O, GUI, and other most basic tasks etc.) and then execute the apps (eg: Games, Multimedia, Content Creation, etc. apps) on an x86 co-processor designed only for PERFORMANCE, not to run menial OS tasks. This way the power usage of an x86 chip is only used when really needed.

Simon- said,
...

YES!
Take that Ninja core
Seriously great idea.
Add some of the compute pipelines that gpus provide as another managed layer and I'm sold.

deadonthefloor said,

YES!
Take that Ninja core
Seriously great idea.
Add some of the compute pipelines that gpus provide as another managed layer and I'm sold.

That is a great idea. Could an application be designed to use both the Xeon phi AND NVIDIA GPUS within a system? Now that would be hardcore. Different instruction sets could be sent to different architectures. Wow.

Open Minded said,
About five years ago, didn't Intel promise 80 core CPUs within five years? 50 cores is isn't 80, Intel! ;-)

These processors don't have 50 cores...

mikeyx12 said,

These processors don't have 50 cores...

FROM THE ARTICLE POSTED ABOVE.... "Every Xeon Phi-equipped PCIe card will mount several 22-nanometer (Ivy Bridge), x86 CPUs for a total of more than 50 computing cores and a “minimum” of 8 Gigabytes of GDDR5 RAM."