Innovative Scheduling Techniques Speed Chip Fabrication


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Innovative Scheduling Techniques Speed Chip Fabrication

By Jay Lyman

NewsFactor Network

July 30, 2002

http://sci.newsfactor.com/perl/story/18801.html

With the typical cost of a semiconductor manufacturing plant at between US$2 billion and $3.5 billion, pressure is heavy to maximize production of the integrated circuits found in everything from alarm clocks to PCs to automobiles.

Full-time chipmaking is hampered by random equipment failures, scheduled tool maintenance, scarce auxiliary resources and the duration and nature of operations that run day and night, but researchers at a consortium that includes the University of Arkansas believe they can boost productivity and cut costs using innovative scheduling methodologies.

The research team is developing scheduling approaches that incorporate methods to recognize and overcome bottlenecks and breakdowns and also work with existing execution software already being used by chip manufacturers. "Our goal is to make something that is actually used in industry, not to solve an academic problem," said University of Arkansas assistant professor of industrial engineering Scott Mason.

Busy Schedule

Researchers said there are dozens of process "flows" involved in fabricating semiconductors . Within each process flow are some 400 to 600 steps and the use of more than 100 machines, which are expensive and, therefore, shared at different stages of production.

Gartner (NYSE: IT) analyst Martin Reynolds told NewsFactor that with chips taking as long as four weeks to progress through a factory, chip plants run around the clock, and there is little to no downtime or room for service or other interruptions. "It is a challenge," Reynolds said. "We're talking about a very complex process."

Changing to Chunks

Assistant professor Mason told NewsFactor the scheduling work, a three-year project sponsored by International Sematech and the Semiconductor Research Corporation, could improve chip delivery performance by 10 percent.

Instead of focusing on each individual tool, Mason said, the group is decomposing the scheduling problem into smaller, more manageable chunks. "Then, after dealing with the individual chunks, we aggregate them ... Each chunk is a tool group or work station, and we schedule these in order of criticality or importance, so we schedule the bottleneck tools first."

Software Scheduling

Mason said that by reorganizing and adjusting for machine setup and service, chip manufacturers could cut their costs while boosting efficiency.

The scheduling methodologies will incorporate ways to overcome such problems to work with and improve existing manufacturing execution software used by such companies as Intel (Nasdaq: INTC) and Texas Instruments (NYSE: TXN) .

One Wafer a Day

Mason said the complexity of chipmaking, which is increasing even more as manufacturers move from standard 200 mm wafers to 300 mm, could be addressed with scheduling methodologies that would impact the return.

"If we can improve efficiency and throughput by only one wafer a day, it will have a significant effect," said Mason. Mason presented the results of his research in July at the International Conference on Flexible Automation and Intelligent Manufacturing in Dresden, Germany. The consortium is comprised of the University of Arkansas, Arizona State University and three German institutions.

Standardized Schedules

Gartner's Reynolds said that while most larger chip manufacturers are already optimizing fabrication schedules with changes in their software, the University of Arkansas work may bring a standard to the industry and lower costs even more.

"The big manufacturers have all solved this [scheduling] problem, but there may be an opportunity with standard software," Reynolds said. "This is not going to revolutionize the manufacturing of semiconductors, but it could be a useful cost saver."

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