Motorola is preparing a next-generation two-core G4-class PowerPC processor, the company will this week tell attendees of its annual Smart Networks Developer Conference, held in Disneyland Paris. The chip, as yet unnamed - at least in public - will contain two PowerPC cores with AltiVec, Motorolas SIMD engine. It will also contain its own memory controller, capable of connecting to DDR and DDR 2 SDRAM, according to documents seen by The Register.
It will interface with the rest of the system using Rapid IO, the next-generation chip-to-chip bus developed by Motorola, but offered as a standard to the embedded processor industry. Given Motorolas Rapid IO heritage, support for the bus isnt surprising - indeed, on sales collateral produced earlier this year, the companys roadmap features a new chip, called the G4+, with Rapid IO built in.
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News source: The Reg