Western Digital and Kioxia - formerly known as Toshiba Memory Solutions - have jointly announced the sixth generation of their 3D flash memory technology, known as BiCS 6, at this year's ISSCC event. As you'd likely expect, this is the highest density the two companies have ever achieved, but there are also improvements to performance.
The new generation delivers improvements in both vertical and lateral scaling, bringing 162 vertical layers of stacked memory, up from 112 layers in the previous generation. Additionally, lateral cell array density has been increased by 10%, and those two improvements add up to a 40% smaller die compared to the previous technology.
In addition to improving the density, the two companies have also used Circuit Under Array CMOS and four-plane operation, resulting in better performance. You can expect "nearly 2.4 times" better program performance and a 10% reduction in read latency, as well as a significant 66% improvement in overall I/O performance.
On the manufacturing side, the new technology allows a 70% increase in the number of bits produced per wafer, and also reduces the cost per bit. What the announcement didn't specify is when this technology will start showing up in products. When the fifth-generation technology was introduced in January of last year, it was planned to be commercially available in the second half of the year, so we can expect a similar timeframe for this one, though the COVID-19 pandemic may hamper the manufacturing process.
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