Next-gen Thunderbolt 5 reportedly leaks, super-fast 80Gbps transfers await us

Intel announced Thunderbolt 4 last year and the technology can be found mostly on the company"s 11th gen Tiger Lake-based laptops. However, it didn"t boost the maximum transfer rate (40Gbps) over what was already available with its preceding Thunderbolt 3 interface. But it looks like next-gen Thunderbolt 5 will be similar to Thunderbolt 3 and will double the throughput up from the current 40 all the way up to 80Gbps, according to a leaked internal presentation slide from Intel.

The slide which is showcasing Intel"s "80G PHY Technology" was apparently posted on Twitter by the company"s Executive VP & GM of the Client Computing Group, Gregory M Bryant, who is on an internal tour of the Intel Israel Lab. The image however was later deleted by Bryant probably after he realized his mistake but fellow media outlet AnandTech was quick to save it.

Day 1 with the @intel Israel team in the books. Great views…incredible opp to see @GetThunderbolt innovation …a validation lab tour and time with the team…can’t wait to see what tomorrow brings! pic.twitter.com/GKOddA6TNi

— Gregory M Bryant (@gregorymbryant) August 1, 2021

As noted above, Thunderbolt 5 looks to be bringing very high 80Gbps bandwidth still using USB-C, which means the compatibility and adaptability of the next-gen interface should be easy, and according to what the slide says, it will be based on a "novel PAM-3 modulation technology".

PAM-3 or three-level Pulse Amplitude Modulation can transfer three bits of data (-1, 0, +1) in two cycles/ unit intervals, exhibiting an efficiency of one and a half (1.5) bits per cycle. This is 50% higher than single-cycled Non-return-to-zero (NRZ) or PAM-2 (two bits: 0 and 1) which is used in current Thunderbolts. However, this still doesn"t explain the rest of the gains so there could be more at play here.

Apparently, the test chips for the new 80G PHY to be used in Thunderbolt 5 are showing promising initial results and these test chips might be built using TSMC"s 6nm FinFET (N6) process but this has not been confirmed yet.

Source and image: AnandTech

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