Intel fabricates next-gen 65-nm and EUV masks

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Intel fabricates next-gen 65-nm and EUV masks

By Anthony Cataldo

EE Times

(01/15/03 10:14 p.m. EST)

SANTA CLARA, Calif. ? Despite the chip industry's hand-wringing about the cost of making photomasks, Intel Corp. said it wants to keep making its own masks and promised to not let them stand in the way of rolling out a new process technology every two years.

To that end, the company announced Wednesday (Jan. 15) that it has started making its first mask sets for the 65-nanometer process technology node and expects to finish making a "device quality" mask this quarter, so it can start evaluating features typically used in its microprocessors. Intel, which plans to start making microprocessors using 90-nm design rules this year, expects the 65-nm process to be ready for production by 2005, officials said.

At the same time, the company said it has fabricated its first masks geared for the 32-nanometer node, which will be based on future extreme ultraviolet (EUV) lithography techniques. The company is leaning on suppliers to provide blank mask substrates and tools to build its own EUV masks, and expects to be the first company to put EUV onto the production line in 2007.

Intel and other chip makers have a lot riding on their mask-making ability. The mask set for a chip must be ready at least a year before production starts, but "mask complexity is increasing faster than device complexity," said Barry Lieberman, engineering manager at Intel's internal photomask unit, dubbed the Intel Mask Operation.

This situation arose in 1997, when companies like Intel and memory chip vendors pushed their lithography tools to the point that the wavelength of light they projected exceeded the minimum feature size of the transistors.

"Wavelength scaling hasn't kept up with the rate of feature size scaling. It takes longer than two years ? typically two generations," Lieberman said.

One way to correct this is to use bigger lenses, but lenses can only get so large to keep aberrations to a minimum. The maximum numerical aperture (NA) is 1, and the biggest lenses today already have an NA of 0.8, Lieberman said.

The only practical way to keep up with Intel's two-year process technology cycle is to keep pushing the lithography tools no matter how fuzzy the image gets and find ways to correct the image. This is known as pushing the K1, also known as the "process complexity" or "lithography aggressiveness" factor. K1 is the product of device feature size and lens size divided by the wavelength of the light source, so lowering the K1 factor is the goal here. The theoretical limit for K1 is 0.25; Intel claims it has brought it down to 0.4.

One way to correct the image is through optical proximity correction, which involves adding extra rectangles to the mask image so that the final exposure on the wafer looks more like the intended image. Another way is through special masks called phase-shift masks.

The problem with jerry-rigging an image in this way is that it makes it tougher for the engineers making the masks. A 90-nm device, for example, needs 200 gigabytes of data to describe a mask with 22 to 25 layers, which translates into some 1 trillion pixels. Finding and repairing a significant defect in such a mask is like hunting for basketballs in an area the size of California, Lieberman said.

Even after making repairs, mask makers can expect just 50 to 70 percent of the masks they make to be production grade. The rest must be discarded. The final tab for making a 90-nm mask set: anywhere from $800,000 to $1.3 million, he said.

This problem is having a huge ripple effect on the mask making industry. Intel estimates the mask industry will is anywhere from $800 million to $1 billion shy of the R&D funds it will need to keep up over the next few years. And many IC manufacturers that used to build their own masks in captive mask shops are now partnering with third-party mask producers.

Intel, however, said it will keep making its own masks internally. Despite the high cost of making masks, the company says it has the money to keep funding its own mask-making efforts and thinks it has some competitive advantages to boot. These include an automated defect management system, a unique E-beam mask correction system, a streamlined supply chain and a close working relationship with the product groups.

Intel also plans to make its own EUV masks, starting with the 45-nm generation set to roll in 2007. At that point, the company will be worried less about K1 factor and the effects of optical proximity correction because the wavelength from the light source will again fall below device feature size. Rather, it will have to work hard to make sure it can make masks with 40 defect-free layers of molybdenum silicon used to reflect a chip's image, officials said.

http://www.siliconstrategies.com/story/OEG...EG20030115S0048