Okay, so I've been kind of putting off learning linked lists for a couple of days because I hate learning things that I don't completely understand... but I finally decided to just jump in and go with it.
I am following a tutorial from Stanford's Computer Science department and have basically copied the tutorial code (except changed 'head' to 'root', just to be different :))
#include <iostream>
using namespace std;
struct node {
int data;
struct node* next;
};
struct node* buildNodes() {
struct node* root = NULL;
struct node* second = NULL;
struct node* third = NULL;
//allocate three nodes in the heap
root = malloc(sizeof(struct node));
second = malloc(sizeof(struct node));
third = malloc(sizeof(struct node));
root->data = 1;
root->next = second;
root->data = 2;
root->next = third;
root->data = 3;
root->next = NULL;
return root;
}
int main() {
}
Okay, I'm starting to understand this a little more... except I have no idea why my compiler (Bloodshed's Dev-C++) gives me the error "invalid conversion from 'void*' to 'node*'." (it points to the lines using the malloc() function).
hmm.... I could have sworn
struct node* root = NULL;
would make 'root' the type 'node'. I really have very little clue about what I'm saying... heh
I don't know, I haven't checked what changed in previous sockets. I agree that the 1156-1155-1151 succession was suspicious, with a reduction in pin count every time. Intel could do a better job of pre-allocating pins for future use. Another hypothesis is that the internal layout of their CPUs change, like the I/O is moved from one place to another on the chip, and they need to reorganize pins rather than having circuitry go into spaghetti mode to remain compatible.
I agree that if AMD is able to maintain compatibility, Intel should be able to do the same, at least by reserving pins for future use and then using those pins when a need for them arises.
However, I wouldn't say that AMD's products are entirely better. Intel's I/O now slightly edges out thanks to having double the bandwidth to the chipset and dedicated Thunderbolt lanes to the CPU. It seems that they could widen their lead with the next platform.
NVMe SSDs have increased the need for PCIe lanes significantly, and AM5 has been pretty underwhelming in that regard, especially because the chipset connection is so narrow and gets saturated with just 1 gen 4 SSD, leaving the other chipset connectivity (Ethernet, Wi-Fi, audio, etc) to hope for any remaining bandwidth. Otherwise motherboard manufacturers could also make more x2 M.2 slots, those would be fast enough at gen 5 speeds and possibly at gen 4 speeds too.
Exactly, the E-cores actually give you good performance for what they offer, it's no surprise that Intel is doubling down on more E-cores instead of more P-cores. The LP-cores are good for when you're system is just sitting there idle and waiting to be used. Every core has it's place tbh, it's just up to Intel to and MS to work to get the scheduler right.
Question
generalt
Okay, so I've been kind of putting off learning linked lists for a couple of days because I hate learning things that I don't completely understand... but I finally decided to just jump in and go with it.
I am following a tutorial from Stanford's Computer Science department and have basically copied the tutorial code (except changed 'head' to 'root', just to be different :))
Okay, I'm starting to understand this a little more... except I have no idea why my compiler (Bloodshed's Dev-C++) gives me the error "invalid conversion from 'void*' to 'node*'." (it points to the lines using the malloc() function).
hmm.... I could have sworn
would make 'root' the type 'node'. I really have very little clue about what I'm saying... heh
any ideas?
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