Official WWDC thread


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The G5 is designed for dul processor systems. It offers 215 in-flight instructions (the G4 can only do 16), an optimized Velocity engine, two double precision floating points, two fload store units, massive branch prediction logic, 130 nanometer process, silicon on insulator, and 8 layer copper interconnects. [14:18 ET]

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YAAAAAAAAAAAAAAAAAAAAAAAAAAAAAY!!!!

#:p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p

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Pretty Damn sweet, thats all I have to say about this. :woot: :woot: :woot: :woot: :jump: :jump: :jump: :jump:

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YAAAAAAAAAAAAAAAAAAAAAAAAAAAAAY!!!!

#:p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p :p

sell teh pc & get new mac!!!111

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An entirely new architecture. Massively parallel. A twelve-unit core with up to 215 in-flight instructions (the G4 is capable of only 16). Optimized Velocity Engine with dual pipeline design and two double precision floating point units. Two fully symmetric integer units and two load and store units. Massive branch prediction logic. "I don't know what it does," Steve says. "Predicts branches. It's a good thing." Lots of laughter. "IBM has done a phenomenal job on this . . . they also happen to hve the world's most advanced chip fabrication." 130 nm process, silicon on insulator, eight-layer copper interconnects, 58 million transistors, and it's built on 300 mm (12-inch) wafers. He displays one of them. "It's just amazing."

[ 11:17 ]The G5s are built in a $300 million facility in East Fishkill, NY. Some microscope views of the chip itself, as well as the giant 12-inch wafers. Some internal shots of the fab. It looks very 2001: A Space Odyssey. Or something. Steve now introduces John Kelly III, Senior VP, Technology Group, IBM.

[ 11:19 ] John Kelly recaps the G5 a little, noting how they took inspiration from their high-end (one would assume POWER4) chips. Some geeky specs that I won't recap here, and I'm sure are available elsewhere. "This is just the beginning," Kelly says. IBM spends $5 billion annually on R&D, much of it toward microprocessor and semiconductor technology. Hundreds of IBM engineers are already working on the next generation. Kelly thanks Jobs and exits. Huge applause.

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lol, please powerbook, please powerbook, please powerbook, please powerbook, please powerbook, please powerbook, please powerbook,

:D lol

This is so tense

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lol, please powerbook, please powerbook, please powerbook, please powerbook, please powerbook, please powerbook, please powerbook,

Tower always comes first. :p

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"We've been waiting for this day for a long time," Jobs says. (Gee, you think?) "Now, let's build a system with it." The G5 system controller was designed by Apple. It's got dedicated bandwidth to main memory for each system. The G5 has a 1 GHz bus for 8 GB/sec of bandwidth. A bi-directional 64-bit bus. And you can add a second processor, which is where the independent buses come into play. Now you ahve 16 GBps of bandwidth and 12 times the bandwidth of the G4. No slowdown when you add a second processor. For memory, they went iwth 400 MHz, 128-bit DDR memory. This allows for 6.4 GB/second of bandwidth. For graphics, AGP 8x Pro graphics. The latest chips from NVIDIA and ATI and power for professional cards.

[ 11:23 ] I/O. 133 MHz PCI-X slots for 2 GBps of bandwidth. One 133 MHz slot and two 100 MHz slots. Storage? Serial ATA, and connects to HyperTransport interconnect.

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The system: Uses the G5 System Controller - among the world's fastest ASICS. The machine has 8GBps bandwidth, with DDR, and much more. Completely independent processors. Uses 400 MHz 128-bit DDR memory. AGP 8x Pro graphics - uses the latest chips from NVIDIA and ATI. 133 MHz PCI-X slots. One 133 MHz slot, two 100 MHz slots. Serial ATA drive connection technology, utilizes HyperTransport. FW 800/400, USB 2.0, Gigabit Ethernet, AirPort Extreme, Bluetooth, and Optical Audio.

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