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Intel and DARPA partner to advance domestic ASIC chips

Intel&039s newest leading-edge manufacturing facility is Fab 42 in Ocotillo Arizona

Intel and DARPA have announced a new partnership to advance the development of Application Specific Integrated Circuit (ASIC) chips made in the United States. The company said that the ability to create cutting-edge ASIC hardware is critical to the country and the pair hope the Structured Array Hardware for Automatically Realized Applications (SAHARA) partnership will help the U.S. stay ahead.

With SAHARA, the partners want to “dramatically shorten” the time it takes to design new ASIC chips through automation. The pair also want to add security features so that the hardware can be safely manufactured in zero-trust environments. Serge Leef, a program manager at DARPA’s Microsystems Technology Office explained that Intel will eventually manufacture the ASICs on its 10nm process.

Discussing the partnership, José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group, said:

“We are combining our most advanced Intel® eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process.”

To allow for the manufacture of the ASICs in zero-trust environments, Intel said it will also work with the University of Florida, Texas A&M, and the University of Maryland. Together, they will build security technologies that protect data and intellectual property from being reverse engineered or counterfeited. The security measures will be tested by teams at the universities who will use various attack strategies to bypass the security measures.

In addition to SAHARA, Intel announced that it was working with Microsoft and DARPA last week on the DPRIVE project which involves developing a hardware accelerator that can boost fully homomorphic encryption computing. This will allow for the analysis of encrypted data without ever actually needing to decrypt it.

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