Here are more details on AMD's big.LITTLE CPU architecture leak

Pretty much like Intel is doing, AMD too has been working on its own hybrid processor architecture consisting of big and little cores. We came to know about this from a leaked patent last year (via @Underfox3). Today we have new information on the development as Twitter user @Kepler_L2 has spotted one of AMD's new patents related to big.LITTLE published a few days back.

The patent outlines how task processing between the two types of cores would be handled in this hybrid approach.

AMD bigLITTLE architecture design

According to this patent, the little cores will have a time threshold built-in and sensors will monitor the length of time it runs at its full clock speed. Once the threshold is crossed, the task will be handed over to the big core. A similar process would be carried out for memory-intense workloads if it runs at its highest frequency state for higher than the threshold time.

That's because the idea behind the use of the little cores is to save power and running them at full speeds for long durations defeats that purpose.

For the big cores, the implementation is exactly the opposite. In essence, if a workload running on the bigger core does not cross the threshold, the task is sent to the little cores since clearly so much processing power does not seem to be necessary for the workload.

Going back to the patent from last year, the architectural block diagram of the big.LITTLE design approach was described in it.

DIagram showing AMD bigLITTLE core plan

Both the cores will have their own dedicated L1 cache but they will share the pool of L2 between them.

Source: @Kepler_L2 (Twitter) | Images via FreePatentsOnline (1), (2)

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