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Intel's 10nm Cannonlake processors delayed to late 2018

Intel has been having a bit of trouble with its 10nm Cannonlake chips, already twice delaying shipments to mid-2018. Now, sources within the supply chain are saying Intel has yet again pushed the ship date back to late 2018, giving some vendors pause as to whether the chip is worth the wait.

The sources have told DigiTimes that the delay in the shipment of the processors is causing many manufacturers to consider skipping the Cannonlake altogether to wait for the release of the 9th-generation Ice Lake 10nm-process chips. DigiTimes said that many notebook vendors have started their 2018 notebook request for quotation (RFQ) processes, but now are forced to shift gears with the Intel delay.

As if to tease vendors on what to expect, Intel showed off a wafer-thin Cannonlake chip at its Technology and Manufacturing Day in Beijing yesterday. Cannonlake is the first chip to use the 10nm manufacturing process, with predecessors Kaby Lake and Coffee Lake using 14nm.

Intel's Stacy Smith, group president of manufacturing and sales, said that the chip continues Moore's Law of more functionality and performance in an ever-shrinking size.

A slide during the presentation from the Beijing event, spotted by Patently Apple, shows Intel pushing its 10nm process later than previously announced, possibly even into 2019. The 10nm Cannonlakes were originally supposed to start shipping later this year.

via Patently Apple

Intel is not the first company to use the 10nm process, as companies such as MediaTek, Qualcomm, and Samsung use it for their mobile devices, but, according to Hot Hardware, Intel said in Beijing that its 10nm process is a "full generation ahead" in terms of transistor density and performance, with Intel Senior Fellow Mark Bohr stating:

"Moore’s Law, as stated by our co-founder over half a century ago, refers to a doubling of transistors on a chip with each process generation. Historically, the industry has been following this law, and has named each successive process node approximately 0.7 times smaller than the previous one—a linear scaling that implies a doubling of density. Thus, there was 90 nm, 65 nm, 45 nm, 32 nm— each enabling the packing of twice the number of transistors in a given area than was possible with the previous node. But recently—perhaps because of the increasing difficulty of further scaling—some companies have abandoned this rule, yet continued to advance node names, even in cases where there was minimal or no density increase. The result is that node names have become a poor indicator of where a process stands on the Moore’s Law curve."

No matter how improved the chip process may be, it won't mean much if Intel cannot get it in the hands of vendors.

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