Pipeline changes could slow Intel's Prescott down

THERE ARE RUMOURS on a number of websites that Intel has re-engineered its architecture to include additional pipelines but if this turns out to be true it may well slow the chip down, not speed it up. Intel is on record as saying in September that the Prescott, its forthcoming successor to the Northwood Pentium 4, as evolutionary and not revolutionary.

Northwood Pentium 4s have 20 stage pipelines, but double a number of critical resources including the L1 D-cache, the L1 I cache, the register re-name table, the and the branch prediction table. If it does support any element of 64-bits, which again is still only speculation, that again would be doubling some registers and paths on the chips. But it seems that the heat problems that the Prescott suffered from earlier this year has forced Intel to re-make the chips masks, with additional stages in the pipeline to get rid of the double clocking of the chip circuitry and the L1 cache decode.

That, however, will have an impact on the performance of the processor, if it turns out to be true. Branch prediction misses will cause a lot more trouble, for example. And, again, if this is correct, it will mean that any performance increases Intel might have got, the increased internal tables could well hold up additional instructions which are shuffling through the processor. Where does Intel go from here with the Pentium 4 architecture? It's evident that if Intel wants to keep up not only with AMD's Opteron but also with chips such as its own Pentium M, a very serious redesign of a flagship desktop processor must be on the cards.

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News source: The Inq

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