Samsung Develops Highly Efficient Stacking Process for DRAM

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Samsung Electronics has announced that it has developed the first all-DRAM stacked memory package using 'through silicon via' technology, which will soon result in memory packages that are faster, smaller and consume less power. The new wafer-level-processed stacked package consists of four 512 megabit DDR2 DRAM chips that offer a combined 2 gigabits of high density memory. Using the TSV-processed 2Gb DRAMs, Samsung can create a 4GB DIMM based on advanced WSP technology for the first time. "The innovative TSV-based MCP (multi-chip package) stacking technology offers next-generation packaging solution that will accommodate the ever-growing demand for smaller-sized, high-speed, high-density memory," said Tae-Gyeong Chung, vice president, Interconnect Technology Development Team, Memory Division, Samsung Electronics.

Samsung's WSP technology forms laser-cut micron-sized holes that penetrate the silicon vertically to connect the memory circuits directly with a copper filling. This removes the need for gaps of extra space and wires protruding beyond the sides of the dies, allowing a significantly smaller footprint and thinner package. Inside the new WSP, the TSV is housed within an aluminum pad to escape the performance-slow-down effect caused by the redistribution layer. Samsung's WSP technology resolves the concerns that MCPs with high-speed memory chips would suffer from performance limitations when connected using current technologies. Samsung's proprietary wafer-thinning technology, announced last year, has also been applied to improve the thin-die-cutting process, essentially eliminating potential physical distortion.

News source: Physorg

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