We recently reported on TSMC’s plans to ramp up production of their 7nm+ node using extreme ultraviolet (EUV) lithography, as well as risk production of a new 5nm node, both during 1H-2019. Not the one to sit idly by, Samsung has also announced significant updates to its process technology roadmap at its third annual U.S. Samsung Foundry Forum.
Although the roadmap makes references to the 3nm node, details are light and even risk production is likely several years away. In the near term though, Samsung’s 7nm Low Power Plus (7LPP) process using EUV lithography should be ready for production during 2H-2018, with parts based on the new process entering mass production beginning 1H-2019.
Samsung seems to have dropped plans for its 6LPP and 5LPP processes, which have now been replaced by a 5nm Low Power Early (5LPE) process, expected to leverage on breakthroughs made with the 7LPP process, focusing on maximizing areal density and lowering power consumption. The 5LPE process will eventually transition to the 4LPE/LPP process built on the 4nm node.
As Fin Field-Effect Transistor (FinFET) technology reaches scaling and performance limitations, Samsung is developing its next-gen fabrication process dubbed Multi-Bridge-Channel FET (MBCFET), based on Gate-All-Around FET (GAAFET) technology. Samsung will use MBCFET technology for its 3nm node, which has been in development since 2002. Other technical details are scant at the moment, but 3nm production is not expected to commence until after 2022 at the earliest. As far as near-term timelines are concerned, 5nm FinFET production should commence in 2019 and 4nm FinFET production should begin in 2020.
Meaningfully advancing its chip fabrication roadmap is extremely important for Samsung – as a vertically integrated company, its appliances, consumer devices, SoC, memory and countless other divisions are strategically poised to reap the benefits of smaller, high-performance, low-power silicon. It will be interesting to see the magnitude of performance and power consumption delta on parts designed on nodes 5nm and beyond, compared to current-gen parts on the 10nm/7nm nodes.