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Xeon Phi, Intel's new “co-processor” for supercomputing

The supercomputer and “high performance computing” (HPC) market is steadily growing, and Intel wants to cut a large piece of the cake with its new line of specifically tailored products named Xeon Phi.

The new Xeon Phi “co-processor” is the final stage of the Larrabee project, ie the idea to use the familiar x86 microarchitecture and instruction set to build a powerful, easily exploitable “processing unit” to couple with a more traditional CPU for executing highly parallelized workloads.

Intel now defines Larrabee as the Many Integrated Core Architecture (MIC), while Xeon Phi is the first commercial fruition of the aforementioned MIC technology: the “accelerating unit” will be first available at the end of 2012 with “Cascade”, the new supercomputing unit from Cray.

Every Xeon Phi-equipped PCIe card will mount several 22-nanometer (Ivy Bridge), x86 CPUs for a total of more than 50 computing cores and a “minimum” of 8 Gigabytes of GDDR5 RAM. “Beyond its compatibility with x86 programming models”, Intel’s press release says, the “Xeon Phi coprocessor will be visible to applications as an HPC-optimized, highly-parallel, separate compute node that runs its own Linux-based operating system independent of the host OS”.

Intel highlights how well its currently available line of Xeon CPUs performed in the most recent edition of the Top500 list ranking the world’s most powerful supercomputers, in which nearly 75% of the systems were equipped with thousands of processors from Santa Clara. With Xeon Phi, Chipzilla wants to secure its place among the HPC players against IBM’s Blue Gene supercomputing machines based on the Power architecture.

Source: Intel’s press release.

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